Towards a Modeling Synthesis of Two or Three-Dimensional Circuits Through Substrate Coupling and Interconnections: Noises and Parasites

Manufacturers introduce more and more remarkable electronic devices into the market allowing the user to surf the Internet, read e-mails, exchange files and watch (HD)TV on smart mobiles phones or PDAs (Person al Digital Assistants) set-top-boxes. These multitask devices require high performance ICs including powerful processors, huge memory capabilities. Therefore, innovative solutions have to be developed to overcome conventional 2D IC performance issues: high RC interconnect delay, thermal heating and power consumption, high integration density, small form factor, reduced packaging, increased yield and reliability, flexible heterogeneous integration and reduced overall costs. In this way, 3D stacking and high aspect ratio vertical interconnects, so-called Through Silicon Via (TSV), have recently attracted much attention to improve performance of ICs at lower cost.

Many different architectures have been proposed, but whatever the 3D approach (i.e. via first, via last…), TSVs play a key role and have to transmit a wide range of potentially high frequency signals (digital, power, analog, RF…). According to this signal diversity, it is mandatory to extract TSV characteristics, for instance its parasitic resistance, inductance, capacitance and conductance on a wide frequency range, highlighting the requirement for frequency dependent electrical models.

This work investigates substrate-coupling effects in mixed IC’s, specially the perturbations on RF blocks. The design and analysis of fully integrated radiofrequency Voltage Controlled Oscillators (VCOs) are key points in RF analysis. First of all, the oscillation frequency sensitivity functions of tuning voltage, bias current and spurious side-bands due to injected noise are extracted to find out some relation between substrate noise and spectrum purity.

In the goal to realize quantum nanometric devices, for instance, based on a resonant tunneling effect through the Si/SiO2 interface, we model SiO2/Si/SiO2 double barriers embedded between two n-doped Si layers. To study the quantum confinement in Si QW we have solved a set of coupled Schrödinger–Poisson equations simultaneously.

In the core of the paper, we try to develop quantitative predictions about the phase noise of such oscillators, and to give some new tracks in this field.

Mixed mode simulations are involved by applying a microscopic Drift Diffusion Model to the device, while the Kirchhoff’s laws govern the rest of the circuit used.

Another problem field for the designers of complex heterogeneous circuits is to predict the perturbations coming from commutating logical gates blocks, flowing through the substrate to reach some sensitive analog blocks. We present an application of a stochastic process model; the digital switching activity is handled as functions defined as Markov Chains.

The electric performances of devices such as MOS or SiGe HBT, specified for analog and analog-digital circuits and working in the radiofrequency range, can be penalized by the presence of defects inherent to the complex structure shrinking. This work is focused on the identification of defects responsible for the current fluctuations at the origin of low frequency noise (LFN) or Random Telegraphic Signals in industrial submicronic BiCMOS technologies. For instance, Gummel characteristics are simulated in order to identify generation-recombination or trap assisted tunnelling process in the base current.

From theoretical point of view, numerical method for analysing heterostructure semiconductor devices is described. Simulations and modeling both have to be performed and followed by electrical parameter extraction. Often, this noise can be very inconvenient since, from non-linearities, it is cumbersome for circuits, systems, working with such devices in the radiofrequency range. It is worth noticing that LFN characterization is not only a useful tool to analyze complex devices, but it seems indispensable at circuit and system level.

In autonomous, complex circuits, it is more and more necessary to introduce some HV voltage blocks (around 50V: for automotive, photo sensors,). Two technologies are proposed to implement the smart power integrated circuits. The first is the well known planar integration using the deep trench isolation (DTI) technique, and the other one is the new stacked 3D integration using through-silicon vias (TSVs) and re-distribution layers (RDLs). Deep trenches filled with silicon dioxide and polysilicon are suggested to achieve the electrical isolation between the power devices as well as between the power devices and low-voltage CMOS parts. For 3D integration technique, two and three-dimensional TCAD-based simulations of TSV or RDL induced coupling, are investigated on the sensitive regions of the CMOS inverter. Moreover, at very high frequency, it seems necessary to consider the parasitic signal as waves. The studies are done directly in the frequency domain or in the time one: a Finite-Difference Time- Domain method (FDTD) is applied to the analysis of two or three-dimensional interconnect structures. Electric and magnetic field distributions and pulse propagations along vias are presented. The scattering parameters for various cases are calculated and compared. Some key issues of this work are an insight on crosstalk or shielding phenomena between lines just as some electromagnetic behavior of vias. The FDTD technique is also adopted to analyze the entire 3-D structure of interconnect, including the lumped devices.

Electrical behavior of 3D interconnections (redistribution metal lines, through silicon via.,) used in 3D IC stack technologies is explored in this chapter. To well understand the interconnection incidence on 3D system performances, it is important to consider the whole electrical context of the 3D application, including the silicon substrate. As an emerging technology, electrical compact models are needed, notably for 3D interconnects which include Through-Silicon Via, to evaluate with precision 3D systems performances. However, 3D interconnects introduce several challenges in modeling. As a matter of fact, they imply considering the whole electrical context by taking into account for example current paths, couplings between interconnections, couplings with the substrate. Example of simple closed-form expressions describing electrical model of 3D ICs propagation lines is reported. We investigate models of high aspect ratio TSV, on both analytical and numerical methods electromagnetic simulations and RF measurements. This model enables to extract substrate and TSV impedance and parasitic elements. Its full compatibility with SPICE-like solvers should allow an in depth investigation of TSV impact on circuit performance.

Considering the modeling: from any point source, we calculate the impedance spreading out. For this, our approach is, at least, twofold: compact Green function or Transmission Line Model, over or into a multi-layered substrate, is derived by solving Poisson's equation analytically. Rapid evaluation uses the Discrete Cosine Transform and its variations. Using this technique, the substrate coupling and loss in IC's can be analyzed. The algorithms permit to extract impedances between any numbers of embedded contacts. Comparisons are performed, using finite element methods and experiments.