In autonomous, complex circuits, it is more and more necessary to introduce
some HV voltage blocks (around 50V: for automotive, photo sensors,). Two
technologies are proposed to implement the smart power integrated circuits. The first is
the well known planar integration using the deep trench isolation (DTI) technique, and
the other one is the new stacked 3D integration using through-silicon vias (TSVs) and
re-distribution layers (RDLs). Deep trenches filled with silicon dioxide and polysilicon
are suggested to achieve the electrical isolation between the power devices as well as
between the power devices and low-voltage CMOS parts. For 3D integration technique,
two and three-dimensional TCAD-based simulations of TSV or RDL induced coupling,
are investigated on the sensitive regions of the CMOS inverter. Moreover, at very high
frequency, it seems necessary to consider the parasitic signal as waves. The studies are
done directly in the frequency domain or in the time one: a Finite-Difference Time-
Domain method (FDTD) is applied to the analysis of two or three-dimensional
interconnect structures. Electric and magnetic field distributions and pulse propagations
along vias are presented. The scattering parameters for various cases are calculated and
compared. Some key issues of this work are an insight on crosstalk or shielding
phenomena between lines just as some electromagnetic behavior of vias. The FDTD
technique is also adopted to analyze the entire 3-D structure of interconnect, including
the lumped devices.
Keywords: Smart integration, device, Electromagnetic parasites, EM coupling,
TVS, RDL, Maxwell equation, 2D, 3D, Finite element method (FEM), Finite
Difference in Time Domain (FDTD), transport equation, simulations, modeling,
Crosstalk, S-parameters.
