Recent Topics on Modeling of Semiconductor Processes, Devices, and Circuits

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To cope with the printability of smaller transistor and interconnect features in semiconductor integrated circuit manufacturing, the area of lithography has seen significant advancements over the last decade. In this chapter, we briefly go over these advancements while giving more weight on recent advancements and methods or those that have prevailed over the time. As particular examples for the recent developments, we review the area of double patterning lithography.

Variability of interconnects is a major problem. Starting with 32nm technology, double patterning lithography is used for printing interconnects in critical layers. Such a process may introduce additional variability to interconnects. In this chapter, we first target interconnect variability for single and double patterning systems at the technology level. Double patterning lithography techniques require additional masks for a single interconnect layer. Consequently, one challenge double-patterning lithography brings is that overlay results in additional variability for interconnect coupling capacitances. We provide variational interconnect analysis methods and extend these techniques to handle variability in double-patterning lithography. We experimentally demonstrate our methodology using technology-computer-aided-design (TCAD) simulations on a 32nm technology.

We then present a parameter reduction-based technique to utilize such variability information for large interconnect networks on integrated circuits. Process variations in modern VLSI technologies are growing in both magnitude and dimensionality. To assess performance variability, complex simulation and performance models parameterized in a high-dimensional process variation space are desired. However, the high parameter dimensionality, imposed by a large number of variation sources encountered in modern technologies, can introduce significant complexity in circuit analysis and may even render performance variability analysis completely intractable. We address the challenge brought by high-dimensional process variations via a new performance-oriented parameter dimension reduction technique. The basic premise behind our approach is that the dimensionality of performance variability is determined not only by the statistical characteristics of the underlying process variables, but also by the structural information imposed by a given design. Using the powerful reduced rank regression (RRR) and its extension as a vehicle for variability modeling, we are able to systematically identify statistically significant reduced parameter sets and compute not only reducedparameter but also reduced-parameter-order models that are far more efficient than what was possible before [2,3]. For a variety of interconnectmodeling problems, it is shown that the proposed parameter reduction technique can provide more than one order of magnitude reduction in parameter dimensionality. Such parameter reduction immediately leads to reduced simulation cost in sampling-based performance analysis, and more importantly, highly efficient parameterized interconnect reduced order models. As a general parameter dimension reduction methodology, it is anticipated that the proposed technique is broadly applicable to a variety of statistical circuit modeling problems, thereby offering a useful framework for controlling the complexity of statistical circuit analysis.

Negative Bias Temperature Instability (NBTI) and Channel Hot Carrier (CHC), which is also called Hot Carrier Injection (HCI), are the leading reliability concerns for nanoscale transistors. The de facto modeling method to analyze CHC is based on substrate current (Isub), which becomes increasingly problematic with technology scaling as various leakage components dominate Isub. In this work, we present a unified approach that directly predicts the change of key transistor parameters under various process and design conditions, for both NBTI and CHC effects. Using the general reaction-diffusion model and the concept of surface potential, the proposed method continuously captures the performance degradation across subthreshold and strong inversion regions. Models are comprehensively verified with an industrial 65nm technology. By benchmarking the prediction of circuit performance degradation with measured ring oscillator data and simulations of an amplifier, we demonstrate that the proposed method predicts the degradation very well. For 65nm technology, NBTI is the dominant reliability concern and the impact of CHC on circuit performance is relatively small.

Monte Carlo analysis has so far been the corner stone for analog statistical simulations. Fast and accurate simulations are necessary for stringent time-to-market, design for manufacturability and yield concerns in the analog domain. Although Monte Carlo attains accuracy, it does so with a sacrifice in run-time for analog simulations. In this chapter, we propose a fast and accurate probabilistic simulation method alternative to Monte Carlo using deterministic sampling and weight propagation. We furthermore propose accuracy improvement algorithms and a fast yield calculation method. The proposed method shows accuracy improvement combined with a 100-fold reduction in run-time with respect to a 1000 sample Monte Carlo analysis.

Hierarchical optimization using circuit block Pareto performance models is an efficient and well established approach for optimizing the nominal performances of large analog circuits. However, the extension to yield-aware hierarchical methodology, as dictated by the need for safeguarding chip manufacturability in scaled technologies, is completely nontrivial. We address two fundamental difficulties in achieving such a methodology: yield-aware Pareto performance characterization at the building block level and yield-aware system-level optimization problem formulation. It is shown that our approach is not only able to effectively capture the block performance trade-offs at different yield levels, but also correctly formulate the whole system yield and efficiently perform system-level optimization in presence of process variations. Our approach extends the efficiency of hierarchical analog optimization, improving nominal circuit performance metrics towards yield-aware optimization. Our methodology is demonstrated by the hierarchical optimization of a phase-locked loop (PLL) consisting of multiple circuit blocks.

Engineered strain, or the inclusion of Ultra Large-Scale Integration (ULSI) process technology that intentionally modifies channel strain in a metal-oxide-semiconductor field-effect transistor (MOSFET), is now a common component of high-performance logic chips. Beneficial channel strain physically deforms the crystal lattice and alters the crystal energy band structure, enhancing carrier transport. This transport enhancement can be a significant contributor to the performance uplift in a ULSI technology node-to-node transition.

A side effect of engineered strain is that the physical mechanisms that introduce strain in a MOSFET are affected by the types and dimensions of the physical structures in the MOSFET’s immediate vicinity. Analysis of strain layout dependency is in general a complex three-dimensional problem, however it can be reduced to compact model-compatible form so that circuit designers can evaluate its impact on circuit response. This chapter reviews recent technology, physics, characterization techniques, modeling approaches, and simulation literature in the field of engineered strain compact modeling.

This chapter reviews the recent chip-level statistical leakage power analysis methods. We first show main sources of leakage from a chip, which consists of three main components: subthreshold leakage, gate oxide leakage and junction tunnelling leakage. We then study the leakage variational models and show that one needs to consider both intra-die and inter-die variations with spatial correlations. Then we review recently proposed statistical leakage analysis methods. These methods include the Monte-Carlo based method, the grid-based method, the gate-based spectral stochastic method and the projection-based method. Brief descriptions, as well as the advantages and disadvantages of these methods are also presented in this chapter. Numerical examples are further provided to give quantitative comparisons among these methods.

As the integration density of on-chip transistors increases, high power density exacerbates the reliability of integrated circuits (ICs), limiting their performance. As a result, sophisticated thermalmanagement becomes a key to design reliable and high-performance ICs, which requiring an accurate and efficient thermal simulation framework. However, due to the large computational cost of general-purpose thermal simulators, we need a dedicated one that is optimized for each specific application. In this chapter, first, we will discuss the various thermal simulation algorithms optimized for each target application, particularly at the system and circuit-levels. Second, we present a detailed analytical formula dedicated to circuit-level steady-state thermal simulation. Finally, we compare computational cost of all circuit-level thermal simulation methods in terms of the computational cost.

Off-chip decoupling capacitor (decap) allocation is a demanding task during package and chip co-design. Most existing optimization approaches use the input impedance of package as the constraints. However, our research indicates that such practice may lead to large overdesign, and better solutions can be achieved when noise derived from the time-domain waveform is used as the constraint. To illustrate the point, we start with a basic algorithm using simulated annealing (SA) to minimize the total cost of decoupling capacitors under the constraints of worst case noise. The key enabler for efficient optimization with SA is an incremental worst-case noise computation based on FFT over incremental impedance matrix evaluation. Simple as it is, the complexity of SA still limits the applicability of the method, especially in the presence of large numbers of I/O counts and large numbers of legal decap positions for modern packages. To address this issue, we further propose a fast decoupling capacitor allocation method which uses spectral clustering and partitioning, localized macromodeling and sensitivity based iterative optimization to speedup the decap allocation process. We experimentally demonstrate our methods using package designs from industry

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