Variability of interconnects is a major problem. Starting with 32nm technology, double patterning lithography
is used for printing interconnects in critical layers. Such a process may introduce additional variability
to interconnects. In this chapter, we first target interconnect variability for single and double patterning systems
at the technology level. Double patterning lithography techniques require additional masks for a single
interconnect layer. Consequently, one challenge double-patterning lithography brings is that overlay results
in additional variability for interconnect coupling capacitances. We provide variational interconnect analysis
methods and extend these techniques to handle variability in double-patterning lithography. We experimentally
demonstrate our methodology using technology-computer-aided-design (TCAD) simulations on a 32nm
technology.
We then present a parameter reduction-based technique to utilize such variability information for large
interconnect networks on integrated circuits. Process variations in modern VLSI technologies are growing in
both magnitude and dimensionality. To assess performance variability, complex simulation and performance
models parameterized in a high-dimensional process variation space are desired. However, the high parameter
dimensionality, imposed by a large number of variation sources encountered in modern technologies,
can introduce significant complexity in circuit analysis and may even render performance variability analysis
completely intractable. We address the challenge brought by high-dimensional process variations via a new
performance-oriented parameter dimension reduction technique. The basic premise behind our approach is
that the dimensionality of performance variability is determined not only by the statistical characteristics of
the underlying process variables, but also by the structural information imposed by a given design. Using
the powerful reduced rank regression (RRR) and its extension as a vehicle for variability modeling, we are
able to systematically identify statistically significant reduced parameter sets and compute not only reducedparameter
but also reduced-parameter-order models that are far more efficient than what was possible before
[2,3]. For a variety of interconnectmodeling problems, it is shown that the proposed parameter reduction technique
can provide more than one order of magnitude reduction in parameter dimensionality. Such parameter
reduction immediately leads to reduced simulation cost in sampling-based performance analysis, and more
importantly, highly efficient parameterized interconnect reduced order models. As a general parameter dimension
reduction methodology, it is anticipated that the proposed technique is broadly applicable to a variety
of statistical circuit modeling problems, thereby offering a useful framework for controlling the complexity of
statistical circuit analysis.
