Nano-FET Devices: Miniaturization, Simulation, and Applications (Part 2)

Scope and Challenges of Nano-FET for Digital Circuit Design

Author(s): Jyoti Kandpal* and Swagata Devi

Pp: 215-240 (26)

DOI: 10.2174/9798898810306125010010

* (Excluding Mailing and Handling)

Abstract

Over the previous thirty years, the scaling of complementary metal-oxidesemiconductor (CMOS) technology has stood crucial to the continued advancement of the silicon-based semiconductor industry. However, when technological scaling reaches the nanoscale zone, CMOS devices face several significant challenges, including higher leakage currents, difficulty increasing on-current, massive parameter changes, low yield and reliability, increased manufacturing costs, etc. In order to sustain previous advances, numerous developments in CMOS technologies and device topologies have been developed and put into practice. Simultaneously with these investigations, some innovative nanoelectronic devices, labelled as "Beyond CMOS Devices," are currently intensively investigated and developed as potential replacements or supplements for eventually scaled classic CMOS devices. Despite offering system integration at extremely high densities, these nanoelectronic devices continue to be in their infancy and confront numerous challenges, including high variations and low dependability. The actual implementation of these promising technologies necessitates substantial study at the device and system architectural levels.


Keywords: Fin-FET technology, Nanosheet FET (NS-FET), Semiconductor design, Sub-5-nm technology, Transistors.

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