In the semiconductor industry, the integration of the Complementary-Metal-Oxide-Semiconductor (CMOS) mechanism into Integrated Circuits (ICs) has resulted in a significant rise in the count of transistors on a single chip. This is made possible by shrinking down the size of Metal-Oxide-Semiconductor-Field-Effect-Transistors (MOSFETs). However, scaling can lead to device performance degradation. To address this, advanced MOSFET designs like multi-gate transistors, junction-less transistors, and Tunnel FETs have been proposed, aiming to sustain Moore's Law and support continued transistor scaling in the coming decade. The key principles of this chapter involved in both single and multi-gate FETs include quantum mechanics, carrier transport, and electrostatics. The scaling of transistors to smaller sizes involves considerations of quantum effects, like tunneling and quantum confinement, which have a significant impact on their behavior. Understanding this chapter is crucial for optimizing their performance, enabling further miniaturization, and enhancing the capabilities of integrated circuits. Additionally, it plays a crucial role in advancing the field of nextgeneration electronics and computational devices.
Keywords: Electrostatic integrity, Quantum mechanics, Quantum confinement MOSFET, FET, multi-gate FET, Single gate FET.
