Recent Advances in Semiconductor Device Research and Applications

At the moment, the sector of electronics faces huge bottlenecks in power and performance; the most influential current semiconductor technologies are the FinFETs, TFETs, and devices made of 2-D materials. FinFETs provide better electrostatic control and alleviate short-channel effects, which enable the continuous scaling of ever-smaller technology nodes. TFETs use band-to-band tunneling to realize switching at very low voltages below the thermionic threshold and thus open the path to ultra-low power operation. Two-dimensional material devices, including graphene, transition metal dichalcogenides, and black phosphorus, are known for their extreme mechanical flexibility, high carrier mobility, and good scalability. These technological advances stand to drive the new generation of neuromorphic computing, quantum devices, and ultra-low power Internet-of-Things platforms. Consequently, future research should be oriented towards long-term integration of these enabling technologies to overcome the limitations of silicon - only electronics with sustainability and high performance.

This chapter explores the fundamental concepts of tunnel field-effect transistors (TFETs) as an alternative to MOSFETs for energy consumption. TFETs rely on Band-to-Band Tunnelling (BTBT) to achieve a subthreshold swing below 60 mV/decade, thereby enabling ultralow-power operation. We investigate the operating mechanisms of TFETs, the energy band lineup, and various device architectures, such as heterojunction, double-gate, and doping-less TFETs. The role of materials (such as silicon, germanium, III-V compounds, and two-dimensional materials) in enhancing tunnelling performance is discussed. The major performance figures, such as I–V characteristics and leakage currents, are compared to those reported for MOSFETs. The potential applications of TFETs for low-power digital circuits, analog/RF circuits, biomedical electronics, and hardware security are highlighted. Finally, future prospects of TFET applications in future electronics are also discussed at the end of this chapter. 

Recently, optical sensors that consume low power and provide higher sensitivity are in high demand for various applications, including photodetectors, target tracking, etc.The Field-Effect Transistor (FET) as a photosensor has become increasingly important in human life in this fast-growing modern world. This flexibility with integrated circuits, the ability to downsize geometries, and the ability to provide enhanced sensitivity. This paper reviews an effective photosensor based on TFET, which provides lower power for applications that utilize the BTBT mechanism. Under exposure to incoming radiation, the proposed devices exhibit a higher illumination current, a low threshold voltage (Vth), a sharp sub-threshold swing (SS), and a high ION/IOFF ratio. These characteristics make them highly suitable for achieving optimal efficiency while consuming low power. This paper provides an in-depth examination of TFET-based photosensors, covering everything from device assessment to their application in photo sensing. It includes both qualitative and quantitative analyses of parameters, such as sensitivity, and explores various factors that influence sensitivity by comparing alternative mechanisms and their transfer characteristics. 

Carbon-based Tunnel Field-Effect Transistors (TFETs) are new devices, having special properties of carbon materials, including carbon nanotubes (CNTs), carbon graphene, and graphene nanoribbons (GNRs), to overcome the drawback of the conventional silicon-based TFETs. In this chapter, carbon-based TFETs, their construction, working, and application for low power and high efficiency will be discussed. Moreover, the vital roles of quantum tunneling, ballistic transport, and quantum capacitance in enabling these devices to achieve ultra-low power consumption and high-speed operation are also discussed. The challenges of materials development, device development, and the integration of these devices with the existing technology are also addressed in this chapter. It also discusses possible uses in solar panels, flexible gadgets, and energy-efficient electronic gadgets. Finally, the manuscript outlines the next stage of device optimization, with a special focus on hybrid material systems, and the use of advanced modelling methods. Additionally, it explores the potential consequences of carbon-based tunnel field-effect transistors (TFETs), which are set to revolutionize next-generation nanoelectronics.

The dynamic nature of computing technologies has put classical field-effect transistors (FETs) at the physical and performance frontier. As the semiconductor industry is unable to solve the problems of scaling, power consumption, and heat dissipation, quantum computing has the potential to reinvent the future of computation. This chapter relates to the concept of quantum computing and FETs and how these concepts can be synergistically integrated to propose a new type of device that is known as Quantum-Enhanced Field-Effect Transistors (QFETs). These are machines that exploit quantum-mechanical phenomena such as superposition, entanglement, and tunneling to overcome the drawbacks of classical FETs, delivering previously unknown performance, energy efficiency, and scalability.

Quantum computing quinconal tenets and FETs are re-established, and special focus is given to quantum effects that can be exploited in nanoscale devices. Quantum tunneling, coherence, and spin-based phenomena have been placed under the most important mechanisms, which can be utilized to enhance the operation of the FETs. The chapter introduces novel QFET designs with the use of quantum dots, superconducting material, and topological insulators so as to be able to manipulate quantum states in the transistor platform. These designs are supported by mature simulation models, including quantum transport models and density functional theory (DFT) calculations, which provide details on the behavior of QFETs under various operating conditions.

The performance of QFETs is evaluated through a full set of simulations to compare their performance with that of classical FETs. The results indicate that switching speed, on-to-off current ratio, and sub-threshold swing decrease significantly with QFETs, achieving maximum power gains of up to 50 percent. Quantum coherence increases charge-carrier mobility, and quantum tunneling enables effective current flow even at incredibly low voltages. These results are presented using new figures, tables, and graphs, which demonstrate the benefits of using QFETs in energy efficiency and scalability.

Other fabrication issues related to QFETs, such as the need for high-accuracy control of quantum states and the incorporation of exotic materials like graphene and transition-metal dichalcogenides (TMDs), are also discussed in the chapter. Hightechnology lithography and cryogenic cooling are suggested as possible solutions to these problems, enabling the implementation of QFETs. Moreover, the scalability of QFETs is discussed, and simulations indicate that such devices can be effectively operated at sub-5 nm nodes, enabling their use in future generations of integrated circuits.

Besides performance metrics, the chapter also discusses the possible uses of QFETs in quantum computing, neuromorphic computing, and low-power electronics. Quantum states manipulated by QFETs result in QFETs being the most promising qubit devices in quantum processors, and their power efficiency is comparable to edge computing and Internet of Things (IoT) devices. It also includes integrating QFETs into current CMOS technology, enabling more hybrid quantum-classical computers.

Although the results are promising, there are still several challenges to address. Future research on quantum coherence at room temperature, the reduction of decoherence effects, and reliable fabrication processes are vital areas of study. This chapter also ends with a roadmap of the development of QFETs, in which interdisciplinary teamwork between quantum physicists, material scientists, and semiconductor engineers is important.

This chapter adds to the mass of literature on quantum-enhanced devices as it presents an in-depth discussion of QFETs that are backed by new simulations and experimental evidence, and highlights theoretical understandings. The results highlight the potential of QFETs to revolutionize FET technologies and introduce a new generation of computing technologies by leveraging the drawbacks of classical technologies. This study will lay the foundation for a new era of electronics innovation by bridging the gap between quantum computing and semiconductor devices.

The combination of quantum computing theory and FETs represents a huge leap towards the goal of more efficient, scalable, and powerful computing equipment, and this paper should encourage further research and innovation in this promising area. 

Over the last 20 years, ISFET (Ion Sensitive Field Effect Transistor) biosensors have been recognized to be the most important technology in detecting glucose in non-invasive ways in urine, changing the way blood glucose concentration is measured. In this paper, an attempt has been made to present the development of ISFET-type glucose biosensors as attributed to advances in nanoscience, surface functionalization techniques, and sensor miniaturization, which improved the ability of the sensors to be sensitive, selective, and stable. More specifically, we focus on how graphene, metal oxides, and carbon nanotubes have been used to increase the surface area of ISFET sensors so that there is more contact with glucose molecules, thereby improving the sensitivity. Another serious problem which is obtained with ISFET-based glucose sensors is related to the detection of glucose due to other constituents like urea and creatinine present in urine, which affects the accurate measurement of glucose. Examples of how these challenges have been overcome are discussed in this paper, including surface modification with glucose oxidase enzymes, and the use of molecularly imprinted polymers (MIPs) for enhanced specificity. The paper also discusses the issue of biofouling and the stability of the sensors caused by biological exposure for long periods, and how it can be solved with different coatings and more rigid materials. The paper talks about making ISFET sensors smaller, which allows them to fit into wearable and implantable gadgets for tracking glucose levels all the time. We look at products on the market and examples from clinical studies to show how ISFET technology is being applied in real life. Lastly, we mention future research paths, such as using artificial intelligence (AI) and machine learning (ML) for better data processing and less intrusive glucose monitoring methods. This review stresses the importance of ongoing improvements in ISFET glucose detection to address current issues, reduce costs, and increase acceptance in clinical settings.

This chapter examines 6T, 8T, and 10T SRAM cell designs and their compatibility with 45nm, 90nm, and 180nm technological nodes. It primarily examines the power consumption, speed, and signal strength of SRAM cell designs. The study uses tools to see how each SRAM cell design works under different conditions. For read, write, and hold operations of the SRAM cell designs, it compares the signal to the noise margin. The findings aid in understanding the advantages and disadvantages of each design, using technologies such as 45nm, 90nm, and 180nm to guide future advancements in memory technology.

This chapter focusses on a comparison of SRAM cell design with six, eight, and ten cell designs and discusses them in the context of various technology nodes, such as 45nm, 90nm, and 180nm. The emphasis is put on essential performance aspects, such as power consumption, speed, and signal quality. Through the application of complex analyzing tools, the study examines the performance of each design under the various conditions, specifically the signal-to-noise margin when performing the read, write, and hold operations. The findings are useful in indicating the strengths and weaknesses of each design, giving an insight into the possible impact of different technologies on the future of memory technology. 

In the electronic industry, the development of efficient FET devices with smaller feature sizes, lower power consumption, and improved performance has intensified competition. The key challenge remains in miniaturizing and creating energy-efficient devices. Multi-gate technologies like FinFETs have become a promising solution for further scaling, offering a compact design and superior current control. As technology continuous to progress, its importance increases, especially in narrowing the performance gap between processors and main memory. Therefore, SRAM has an important role in determining system performance, reliability, and power consumption. This chapter focuses on the design of 6T and 8T SRAM cells using a FinFET device. The key considerations in SRAM cell design include size, noise margin, and access time. Therefore, this chapter also explores SiGe-based SRAM cells, analysing their performance regarding noise margin and delay.

In this chapter, an analysis of a split-gate, doping-free heterojunction tunnel field-effect transistor (SG-DG-HJ-TFET) compared with a heterojunction tunnel fieldeffect transistor with a non-split-gate (NSG) architecture will be presented. The Doping-Free Tunnel Field-Effect Transistor (DF-TFET) is a promising next-generation design, offering robustness against random dopant fluctuations and eliminating the need for high-temperature processing and expensive annealing. The performance of both configurations is analyzed and compared in terms of DC performance. Parameters such as drain current, electric field distribution, surface potential, sub-threshold swing (SS), current, etc., are evaluated during this evaluation. The temperature dependency of both the TFET architectures is compared and reported in this work. The Silvaco ATLAS technology is used for two-dimensional design simulation to implement the suggested design. The fabrication flow of the proposed SG-DG-HJ-TFET is also described in detail.

 This chapter studies a hetero-stacked source n-type TFET (HSS-nTFET) using TCAD simulations. The device uses a stacked-source structure with gate–source overlap to improve tunneling. This design increases the electric field at the source–channel junction and reduces the tunneling width, which supports higher current conduction. The electrical performance is analyzed by varying the source stack materials and key device dimensions. Based on the simulation results, the proposed HSS-nTFET achieves an average subthreshold swing of about 20 mV/dec, and an ION/IOFF ratio on the order of 1012. The effect of different gate dielectric materials is also examined, showing that high-k dielectrics improve the ON current and switching performance.

This chapter concentrated on a comprehensive study of TFET with its optical application at three specific wavelengths. Initially, ionic radiation analysis was performed over the Ge-source double gate TFET to evaluate the parameter collected charge (Qc ) and bipolar gain (β). It generated a maximum bipolar gain of 71.6 at LET = 20 MeV.cm2 /mg. After this interface trap analysis, ZHP and hetero stack (HS) TFETs were analyzed, including their effects on the energy band and transfer characteristics. ZHP-TFET reported a major fluctuation in the drain current compared to HSTFET. Further, the impact of noise was evaluated at different frequencies on incorporating various trap effects. Finally, optical assessment of the TFET photo sensor was performed at wavelengths of 300, 500, and 700 nm. Here, HS TFET reported maximum spectral sensitivity (Sn ) compared to ZHP-TFET at low gate voltages. The maximum spectral sensitivity of HS-TFET was observed as 421, and ZHP-TFET showed 125 maximum spectral sensitivity at a wavelength of 300 nm. The complete study of TFET was conducted at low supply voltage with minimal power dissipation. 

This chapter discusses the design, simulation, and performance evaluation of a dielectric-modulated zinc oxide thin-film transistor (DM-ZnO-TFT) biosensor aimed at label-free biomolecule detection. The sensor exploits the dielectric modulation caused by biomolecules with different dielectric constants located within a nanocavity near the TFT’s drain region. To improve stability and enhance molecular binding, a biocompatible Al2O3 layer along with a dielectric SiO2 stack is incorporated. Through 2D TCAD simulations, key electrical parameters such as threshold voltage shift, drain current, surface potential, and transconductance were analyzed. The findings reveal a significant change in device behavior in response to biomolecules with dielectric constants ranging from 1 to 15, demonstrating the sensor’s high sensitivity and realtime detection capabilities. This DM-ZnO-TFT biosensor offers a cost-effective, CMOS-compatible, and promising approach for future biomedical and environmental sensing technologies.

The biosensing potential of a ferroelectric negative capacitance biosensor tunnel field-effect transistor (FENCB-TFET) is investigated in this chapter using a dielectric modulation technique. The design features nanoscale pores near the source and drain regions to enhance the surface area available for biomolecule immobilisation, therefore directly enhancing electrostatic coupling. Adjustments in turn-on voltage, drain current sensitivity, and current switching ratio affect performance. We evaluated biomolecules with neutral, positive, and negative charges at the control layer and at the insulator edge under a range of dielectric conditions. The study takes into account practical limitations, such as partially filled holes caused by steric hindrance, in addition to perfect sensing. The findings show that the FENCB-TFET is a strong, extremely sensitive competitor for low-power, label-free biosensing. 

This chapter provides an extensive description of a Junction-less Double Gate-Tunnel Field Effect Transistor (JL-DG-TFET) digital inverter and demonstrates how it outperforms traditional CMOS-based systems. In this inverter, complementary p-type and n-type JL-DG-TFETs are utilized so that better control over leakage current can be achieved, which improves energy efficiency. The JL-DG-TFET is optimized for low power usage, which is achieved due to the steep subthreshold slope, and the absence of junctions further reduces fabrication complexity. SILVACO TCAD and Cadence Virtuoso tools are used for simulations. Simulation results show reduced leakage power, improved noise margin, and minimized average delay. These outcomes illustrate that the JL-DG-TFET-designed inverter is a promising solution for lowpower, high-performance circuits and helps address scaling limitations in semiconductor technologies.