Moore's law has contributed to a significant factor behind the ongoing
shrinking of transistors in CMOS technology since its inception in the 1960s. Dennard et
al.'s scaling theory from 1974 illustrates how cost, performance, and power can be
enhanced in solid-state devices while maintaining fundamental MOSFET operating
characteristics. In the past, the regulation of dynamic power was governed by Moore's
law. However, as leakage increases with decreasing geometries, quiescent power
consumption becomes the predominant factor in microprocessor design. Short channel
issues like DIBL, SS, and hot electron effect may all have a detrimental influence on
MOS device performance. Because of these effects, CMOS technology has hurdles, and
TFETs may overcome SS limits, making them a promising option for low-power standby
uses. Finally, we discuss the possibilities beyond CMOS technology, detailing the
difficulties and prospects for technological advancement. This chapter gives a brief
summary of current developments in device development with an emphasis on Tunnel
FETs for upcoming circuits.
Keywords: CMOS, MOSFET, TFET, Transistors.
