Title:Design and Analyze the Effect of Hetero Material and Dielectric on TFET
with Dual Work Function Engineering
Volume: 14
Issue: 1
Author(s): Vimala Palanichamy*Arun Samuel Thankamony Sarasam
Affiliation:
- Department of Electronics and Communication Engineering, Dayananda Sagar College of Engineering, Shavige
Malleshwara Hills, Kumaraswamy Layout, Bangalore, 560 111, Karnataka, India
Keywords:
Hetero junction, hetero stacked dielectric, tunnel field effect transistors, drain current, transconductance, MOS transistors.
Abstract:
Background: As the size of the field effect transistors is reduced down to nanometers, the
performance of the devices is affected by various short-channel effects. To overcome these effects,
various novel devices are used. Tunnel Field Effect Transistors (TFET) are novel devices in which
the drain current needs to be improved. Gate engineering and III-V compound materials are proposed
to improve the ON current and reduce the leakage current along with its ambipolar behaviour.
Methods: The proposed device structure is designed with a heterojunction hetero dielectric dual material
gate Tunnel Field Effect Transistor incorporating various combinations of III-V compound
materials such as AlGaAsSb/InGaAs, InGaAs/Ge, InGaAs/InP and SiGe/Si. As in III-V composite
materials like AlGaAsSb/InGaAs, the narrower bandgap at the source channel interface helps to
improve the electric field across the junction. At the same time, the wider bandgap at the channel
drain junction leads to unidirectional current flow, resulting in ambipolar reduction. 2D TCAD simulation
is used to obtain the electrical parameters for Hetero junction TFETs and the comparison analysis
of different Hetero device structures.
Results: The device's electrical parameters, such as energy band diagram, current density, electric
field, drain current, gate capacitance and transconductance, have been simulated and analyzed. Besides,
the dual material used in the gate, such as Metal1 (M1) and Metal2 (M2), along with
HfO2/SiO2 stacked dielectric, helps improve the gate controllability over the channel and the leakage
current reduction.
Conclusion: An ION=10-1A/μm, IOFF = 10-12A/μm at drive voltage 0.5V is obtained for InGaAs/InP
layer at the source channel hetero junction TFET, and ION=10-2A/μm, IOFF =10-14A/μm at drive voltage
0.5V is obtained for SiGe/Si layer at the source channel hetero junction TFET. Therefore, the
InGaAs/InP and SiGe/Si layer TFET are more suitable for ultra-low power integrated circuits.
