Title:Analysis of Lanthanum Oxide Based Double-Gate SOI MOSFET using
Monte-Carlo Process
Volume: 19
Issue: 2
Author(s): Pattunnarajam Paramasivam*, Naveenbalaji Gowthaman and Viranjay M. Srivastava
Affiliation:
- Department of Electronics and Communication Engineering, Prince Shri Venkateshwara Padmavathy Engineering
College, Chennai, 600127, India
Keywords:
Lanthanum oxide, monte carlo simulation, double-gate MOSFET, quantum effects, potential distribution, particle transport, drift velocity, conduction band energy, packing density.
Abstract:
Introduction: This work proposes a Double-Gate (DG) MOSFET with a Single Material
made of Silicon On-Insulator (SOI). The Lanthanum Oxide material with a high k-dielectric constant
has been used as an interface between two gates and the channel. The Monte Carlo analysis has been
used to determine the Conduction Band Energy (Ec) profiles and electron sheet carrier densities (ns)
for a Silicon channel thickness (tsi) of 10 nm at 0.5 V gate drain-source voltages. The transverse electric
fields are weak at the midchannel of DG SOI MOSFETs, where quantum effects are encountered.
The Monte Carlo simulation has been confirmed to be effective for high-energy transport. A particle
description reproduces the granularity property of the transport for nanoscale modeling.
Methods: This work utilizes a Monte Carlo (MC) Simulation for the proposed Double Gate Single
Material Silicon On Insulator MOSFET with (La2O3=2 nm) as dielectric oxide on upper and lower
gate material. The electrical properties of the DG SOI MOSFETs with Lanthanum Oxide were analyzed
using Monte Carlo simulation, including the conduction band energy, electric field, potential
distribution, particle movement, and average velocity.
Results: The peak electric field (E) simulation results and an average drift velocity (υavg) of 6Í105
V/cm and 1.6Í107 cm/s were obtained, respectively. The conduction band energy for the operating
region of the source has been observed to be 4% to the drain side, which obtained a value of -0.04 eV
at the terminal end.
Conclusion: This proposed patent design, such as double-gate SOI-based devices, is the best suggestion
for significant scalability challenges. Emerging technologies reach the typical DG SOI
MOSFET's threshold performance when their geometrical dimensions are in the nanometer region.
This device based on nanomaterial compounds has been more submissive than conventional devices.
The nanomaterials usage in the design is more suitable for downscaling and reducing packaging density.
